1. Field of the Invention
The present invention relates to a delay locked loop circuit used for clock synchronization, multiphase clock generation, multiplication, and the like and, more particularly, to a technique of preventing the loss-of-lock state of a delay locked loop circuit.
2. Description of the Related Art
A delay locked loop circuit (to be abbreviated as a DLL circuit hereinafter) is a circuit for synchronizing the feedback clock output from a voltage controlled delay line (to be abbreviated as a VCDL hereinafter) with a reference clock delayed by one clock in order to establish clock synchronization in a semiconductor integrated circuit chip. Typical malfunctions of a DLL circuit include pseudo-lock and loss of lock. Pseudo-lock is a state in which a feedback clock synchronizes with a reference clock delayed by two or more clocks. The occurrence of pseudo-lock disables multiphase clock generation and multiplication. Japanese Patent Laid-Open No. 2005-020711 discloses a technique of preventing this pseudo-lock.
Loss of lock is a malfunction that causes a DLL circuit to synchronize a reference clock with a feedback clock delayed by 0 clock from the reference clock. Loss of lock will be described with reference to FIG. 13. Referring to FIG. 13, reference symbol CLKIN denotes a reference clock; FBCLK, a feedback clock; Up, an Up-signal from a phase comparator which is used to raise the charge pump (to be abbreviated as CP) output; and Dn, a Down-signal from the phase comparator which is used to lower the CP output. The CP raises and lowers the output voltage in accordance with the difference between the pulse width (the temporal width of a pulse) of the Up-signal Up and that of the Down-signal Dn.
In the DLL circuit, the normal operation of the phase comparator is to phase-compare a leading edge b of the second pulse of the reference clock CLKIN with a leading edge c of the first pulse of the feedback clock FBCLK. When the power is turned on or an external clock signal is disturbed, the phase comparator may phase-compare a leading edge a of the first pulse of the reference clock CLKIN with a leading edge c of the first pulse of the feedback clock FBCLK. This is loss of lock.
In this case, the phase comparator determines that the feedback clock FBCLK is delayed from the reference clock CLKIN. For this reason, the pulse width of the Up-signal Up becomes larger than that of the Down-signal Dn, and the control voltage rises to the highest voltage that the charge pump CP can output. The delay time of the feedback clock FBCLK is fixed to the minimum delay time of the VCDL. However, this fixed state varies in delay time with variations in temperature, variations in power supply voltage, manufacturing variations, and the like, and hence differs from a locked state. This increases the jitter of the feedback clock. That is, the incorporation of the DLL circuit in the chip loses its meaning. For this reason, the DLL circuit preferably incorporates a mechanism for preventing loss of lock. As this mechanism for preventing loss of lock, the methods disclosed in Japanese Patent Laid-Open Nos. 2007-243877 and 11-205102 will be described.
The method disclosed in Japanese Patent Laid-Open No. 2007-243877 uses a DLL circuit and a counter control circuit (CNT). A counter control circuit (CNT) 2 receives a reference clock CLKIN, and outputs a control signal S to activate a DLL circuit 1 after counting one clock. This makes it possible to phase-compare an edge b of the reference clock CLKIN and an edge c of the feedback clock FBCLK in FIG. 13, thereby preventing loss of lock.
The mechanism for preventing loss of lock in Japanese Patent Laid-Open No. 11-205102 makes the voltage of the output line of a low-pass filter (LPF) for low-pass filtering an output from a charge pump circuit higher than an intermediate voltage VR at the occurrence of loss of lock. Therefore, this mechanism compares the voltage of the output line with the intermediate voltage VR by using a voltage comparator. If the voltage of the output line is higher than the intermediate voltage VR, the mechanism outputs a reset signal RST. This resets the phase comparator and the LPF, thereby preventing loss of lock.
The method of preventing loss of lock by using a counter disclosed in Japanese Patent Laid-Open No. 2007-243877 is effective if a VCDL operates in the described manner when the power of a semiconductor integrated circuit chip is turned on. Loss of lock also occurs when an external clock signal is disturbed. In this case, the counter control circuit 2 loses its meaning, and hence the method disclosed in Japanese Patent Laid-Open No. 2007-243877 cannot escape from loss of lock. In general, a DLL circuit includes a pseudo-lock detection circuit. However, this method cannot prevent loss of lock when the pseudo-lock detection circuit detects pseudo-lock and restores the DLL circuit to the initial state. In addition, when the power of the semiconductor integrated circuit is turned on, the potential at an inverter control node in the VCDL is unstable, and hence the VCDL outputs an unintentional clock. For this reason, it is also sometimes impossible to prevent loss of lock when the power is turned on.
The method disclosed in Japanese Patent Laid-Open No. 11-205102 requires a voltage comparator as an analog circuit and an intermediate voltage VR input to the voltage comparator for the detection of loss of lock. The voltage comparator requires a large area for layout because it is an analog circuit, and hence has a large circuit size and consumes higher power than a logic circuit. This comparator requires a resistor or capacitor to generate the intermediate voltage VR. This also makes it necessary for the comparator to have a large area for layout. In addition, in order to reset a phase comparator 3 at a proper timing, a complex circuit is required.